The Welvet 1.7 AI Engine Architecture

This interactive technical analysis breaks down the core execution paradigms of the Welvet AI Engine—an open-source framework developed by OpenFluke (under Samuel Watson) for continuous artificial life simulations and edge intelligence. Welvet eliminates standard machine learning abstractions, rejecting silent hardware fallbacks, avoiding FP32 master tensors during quantization-aware training, and organizing neural graphs into volumetric step meshes across consumer devices.

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Volumetric Step Mesh

Neural operations are mapped across spatial coordinates (Depth × Rows × Cols × LayersPerCell). Double-buffered state resolution at discrete times t and t+1 enables remote cyclic feedback without graph memory corruption.

Topology: Spatial Grid double-buffer

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Storage Truth (`FormatNone`)

Rejects the FP32 master tensor used in traditional QAT. The stored weight precision in physical memory is absolute truth. Native in-dtype SGD applies gradients directly into low-precision memory spaces.

Native Types: 34 Zero FP32 Scratch

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No Silent Fallbacks

Prohibits hidden CPU fallback transfers when an accelerator path is missing. If an NPU/GPU layer is unmapped, execution explicitly halts or skips via manifest, preventing hidden PCIe bus bandwidth bottlenecks.

Hardware Routing: Explicit 7 Native ABIs

Engine Execution Core & ABI Bridge Architecture

Welvet maintains a single Go execution orchestrator that interfaces with high-performance C++ HPC code (`welvet.cpp`), GPU platforms (Metal, CUDA, ROCm, Vulkan, MLX), and Qualcomm Hexagon NPU (`nativeqnn`). Data transfers require explicit synchronization primitives.

[1] GO HOST RUNTIME

Orchestration & State

• Volumetric Step Mesh
• HuggingFace Ingestion
• .entity State Saver

SyncToGo() / SyncToMLX()

[2] DENSE MATVEC CORE

Unified Microkernel

• FormatNone (34 dtypes)
• 20 Quantization Packs
• Plan 9 SIMD Tiling

Zero f32 Inflate Buffer

[3] EXPLICIT ABIs

Native C++ Bridge

• NativeCPU (welvet.cpp)
• libwelvet_qnn (Hexagon)
• welvet.metal / cuda

Hard Errors on Unmapped

[4] PHYSICAL SILICON

Hardware Execution

• Qualcomm Hexagon HTP
• Apple Silicon Unified RAM
• Discrete CUDA/ROCm VRAM

Deterministic Hardware Parity

The Storage Truth Paradigm & In-Dtype Training

Standard deep learning edge fine-tuning uses Quantization-Aware Training (QAT), which forces hardware to maintain a full FP32 (32-bit floating point) master copy of every weight in background memory. Welvet enforces Absolute Storage Truth (`FormatNone`): the weight format in memory is the final truth. SGD updates occur directly in the native precision.

⚠️ Traditional QAT Approach

✕ FP32 Master Tensor: Retains full 4-byte FP32 copy in RAM alongside low-precision active model.
✕ Memory Footprint: Requires 4.5× to 6× the raw weight storage during fine-tuning pass.
✕ Edge Bottleneck: Exceeds mobile/edge VRAM limits on multi-billion parameter models.

⚡ Welvet `FormatNone` Storage Truth

✓ Zero Master Copy: Weights remain locked to physical byte representation (e.g. INT8, FP16, Q4_0).
✓ In-Dtype SGD: Cross-numeric updates apply gradients directly into low-precision memory spaces.
✓ Edge Fine-Tuning: Enables continuous real-time learning on low-power consumer devices.

Interactive Edge Training RAM Memory Footprint Calculator

Select a model parameter size and deployment target format to calculate the exact hardware VRAM required for training on edge devices under Welvet versus traditional frameworks.

Model Size (Parameters)

Target Storage Format

Activation Scratch Overhead

Traditional QAT RAM Needed

0.00 GB

Quantized Model + Hidden FP32 Master

Welvet FormatNone RAM Needed

0.00 GB

In-Place Native Storage Truth Only

Edge RAM Savings

0.00 %

Memory Bandwidth Retained

Empirical Hardware Acceleration Benchmarks

Welvet provides explicit, opt-in hardware routing via dedicated native dynamic libraries (`.dll`, `.dylib`, `.so`) and C ABIs. Below are validated empirical performance figures captured on Qualcomm Snapdragon X Hexagon NPUs and Apple Silicon Metal GPUs.

Snapdragon X NPU Acceleration

nativeqnn ABI 1.0

Execution latency comparison between baseline Go f32 CPU path and direct Qualcomm Hexagon HTP DLL execution (`graphExecute`).

Average Latency Reduction: > 90% to 95% Faster

Apple Metal GPU Speedup (Mamba)

welvet.metal ABI 1

Execution time of Mamba forward passes on Apple Silicon across datatypes. GPU latency remains locked at ~29ms by saturating memory bandwidth.

FP8 Storage Truth Acceleration: 9.1× Speedup vs CPU

Welvet Explicit Hardware Backend Matrix

Backend	Target Platform	ABI / Binding Path	Forward Execution	On-Device Edge Training	Sync Primitive
NativeCPU	Linux / Windows (amd64)	welvet.cpp C ABI	Supported	Supported (NormalBP/MSE)	SyncWeightsFromNative()
NativeQNN	Windows ARM64 (Snapdragon X)	libwelvet_qnn.dll (Hexagon HTP)	Supported	Inference Optimized	Graph Execute Sync
NativeMetal	macOS / Apple Silicon	welvet.metal ABI 1	Supported	Supported	SyncToGo()
NativeCUDA	Linux / Windows (NVIDIA)	welvet.cuda ABI 1	Supported	Supported	SyncToGo()
NativeROCm	Linux (AMD Instinct/Radeon)	welvet.rocm ABI	Supported	Supported	SyncToGo()
NativeVulkan	Cross-Platform Edge GPUs	welvet.vulkan Library	Supported	Supported	SyncToGo()
BackendMLX (v1.7)	macOS / Apple Silicon	libwelvet_mlx.dylib (v1.0)	Forward Only	Explicitly Disabled	SyncToMLX / SyncFromMLX

Volumetric Step Mesh & Bicameral Systems

Welvet structures neural networks spatialized across 3D/4D grid coordinates (Depth, Rows, Columns, LayersPerCell). To prevent cyclic feedback loops from causing memory race conditions, the engine uses a Discrete-Time Step Mesh with double-buffering ($t$ vs $t+1$). Sibling network hemispheres are updated in parallel using Cameral Learning Protocols & `CamSync` weight blending.

Interactive Volumetric Mesh Simulation

Visualizing discrete time-step pulses across spatial cell coordinates. Updates at time t+1 write into buffer memory without corrupting active inference at time t.

Current Time Step: t = 0 State: Buffered Stable

Bicameral Learning & `CamSync` Simulator

Cameral systems utilize sister hemispheres exploring distinct learning rates or tasks. `CamSync` performs post-step inter-cameral weight blending across the spatial mesh.

Hemisphere A (Explorer Expert Weight) 0.850

Hemisphere B (Anchor Knowledge Weight) 0.250

`CamSync` Inter-Mesh Blend Ratio 10% Soft Blend

RECONCILED CAMSYNC WEIGHT

0.7900

Formula: $W_{new} = W_A \cdot (1 - \alpha) + W_B \cdot \alpha$

The `w2a` Automated Validation Suite Inventory

Rather than static python notebooks, Welvet is validated via the companion repository w2a (Welvet Validation & ABI bindings). The framework executes 6,227 total automated checks across 5,689 native backend parity cases (C++, Metal, CUDA, ROCm, Vulkan, MLX, QNN) ensuring strict zero-drift bit parity.

Automated Check Distribution

Breakdown of 6,227 validation cases across w2a suite leaves and engine tests.

6,163 w2a leaves + 64 engine/native tests

Native Parity & Layer Suite Inventory

Category / Suite	Backend / Role	Leaf Cases	Test* Wrappers

Showing 0 validation suites 100% Deterministic Bit-Parity Target